The technology described herein relates to display controllers for data processing systems.
In data processing systems, an image that is to be displayed to a user is typically processed by a so-called “display controller” of the data processing system for display.
Typically, the display controller will read an image or images to be displayed from a so-called “frame buffer” in memory which stores the image(s) as a data array (e.g. by internal direct memory access (DMA)) and provide the image data appropriately to the display (e.g. via a pixel pipeline) (which display may, e.g., be a screen or printer). The image or images to be displayed are is stored in the frame buffer in memory, e.g. by a graphics processor, when they are ready for display, and the display controller will then read the frame buffer and provide the output image to the display for display.
The display controller processes the image(s) from the frame buffer(s) to allow it to be displayed on the display. This processing includes appropriate display timing functionality (e.g. it is configured to send pixel data to the display with appropriate horizontal and vertical blanking periods), to allow the image(s) to be displayed on the display correctly.
The Applicants believe that there remains scope for improvements to display controllers for data processing systems.
Like reference numerals are used for like components throughout the drawings, where appropriate.